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MHZ100Q - Open Source FPGA-based 100MHz A/D

Sampling Rate Conversion using a Cascaded Integrator Comb (CIC) Filter

A cascaded integrator-comb (CIC) desampling filter

One of the design goals was to keep the hardware as simple as possible by putting functions in the VHDL firmware where possible. Using a fixed sampling rate for the A/D converters is one example: multiple hardware sampling rates would complicate the clocking and would also require different antialiasing filters. Therefore, we need to implement desampling and the corresponding antialiasing filters in the VHDL firmware.

The Cascaded Integrator Comb (CIC) filter is an excellent candidate for the firmware implementation. It can run at high speed while using few on-chip resources, and it easily supports multiple sampling rates.


A finite impulse response with unity coefficients

The CIC filter was originally described by Hogenauer; it has been widely used in applications requiring large changes in sampling rate, particularly delta-sigma A/D and D/A converters.

One way to look at CIC operation is to start with a simplified FIR filter in which all coefficients have the same value. Then the impulse response of the filter is a rectangle, and the frequency response is a sin(x)/x shape. If we cascade several of these filters, then the impulse response of the composite filter is the convolution of multiple rectangular responses, and the frequency response is sin(x)/x raised to the n'th power. As shown by the figure at the bottom of the page, a 3-stage filter has is sidelobes substantially suppressed, and makes a good lowpass filter. The frequency response in the passband is not flat, but this can be corrected by later processing.

The key insight for the CIC is that a rectangular filter can be implemented as an integrator followed by a delay-and-difference section (the Comb part). Second, if the comb section is running at a 1/k sampling rate, where k is the filter length, then it becomes a simple differentiator, and reduces to the scructure in the first image.

The adders must be large enough to avoid overflow in the computations. In the conceptual FIR filter, the output can be a maximum of R times the input, so the registers must be at least N+log2(R) bits, where N is the number of input bits. For 3 stages, the register lengths are therefore N+3*log2(R) bits. Taking as worst case desampling from 100MHz to 1 kHz (a factor of 100 000), then the required word length is N+3*log2(10^5) or 8+3*17 or 59 bits. The integrators in the CIC structure will overflow and wrap around, but the subtractions in the comb section will still give the correct result as long as the registers are 59 bits or more.

This first implementation included a mux to bypass the CIC filter when running at the full 100MHz sampling rate. Then I realized that the integrator and differentiator cancel each other out if they are run at the same rate. So, the bypass mux is unnecesary and the CIC just acts as a series of delays in that case.

For lower desampling ratios (ie, higher output sampling frequencies) the registers will then be unnecessarily large. In this application there's little to be gained by supporting multiple register lengths, so the CIC filter always computes with the worst-case number of bits. The gain of the CIC also depends on R, so it is followed by a bit shifter which compensates for this gain and keeps the appropriate most significat bits for further processing.

Impulse and frequency responses for 1- 2- and 3-stage filter cascades

$Date: 2011/11/23 20:40:03 $